Mask Layout Contractor

CUPERTINO, CA

ENGINEERING - ASIC

FULL-TIME - CONTRACTOR

Mojo Vision is pioneering a highly flexible, wafers-in, wafers-out micro-LED platform to unlock AI applications in multiple market segments. Built over nine years by our skilled engineers, our system-level process combines advanced 300mm silicon architecture with GaN-on Silicon emitters, proprietary quantum dots, and micro-lens arrays to solve conventional trade-offs in size, brightness, bandwidth density, and power. Our scalable, manufacturing-ready approach enables breakthrough products such as AI glasses and next-generation optical interconnects.

At Mojo, our team includes talented professionals with expertise in product design, user experience, applied physics, hardware, software, optics, photonics, electronics, chemistry, and vision science.

We are a startup founded by technology experts with decades of experience developing pioneering products and platforms backed by some of the world's leading technology investors in Cupertino, CA.

Roles and Responsibilities:

We are looking for an experienced analog layout contractor to join us full-time from May 2026. The perfect candidate will have extensive experience in analog layout in state-of-the-art FinFet nodes. This role requires deep hands-on layout expertise and a strong understanding of advanced node effects. Familiarity with SKILL coding is a plus. The candidate should have working knowledge of UNIX and be self-sufficient. Communication is key to success in this role.

  • Design and implement complex layout for mixed signal and analog circuits in advanced FinFet technologies (e.g. 5nm, 3nm or similar).
  • Own layout development in IP/block level, with awareness of chip-top integration constraints.
  • Optimize layout for area, matching, parasitics, reliability and manufacturability.
  • Work closely with circuit designers to co-optimize performance, area and robustness.
  • Contribute to methodology improvements, including layout automation and SKILL-based flows.

Required Skills:

  • Proven experience in custom analog layout design in advanced FinFET nodes
  • Strong understanding of layout dependent effects across technology nodes (e.g., LOD, WPE, stress effects) and advanced node constraints such as multi-patterning, fin quantization, and restrictive design rules.
  • Must recognize failure prone circuit and layout structures, have experience with analog and DFM best practices, and proactively work with circuit designer for best approach to problems.
  • Expertise in Cadence Virtuoso (Layout XL or equivalent) and Calibre (or equivalent) for physical verification.

Preferred Skills:

  • Excellent communication skills and ability to work independently in a fast-moving environment
  • Experience with high speed I/Os, image sensors or pixel arrays
  • High level of proficiency in interpretation of Calibre, LVS, DRC, ERC results. Proficiency in SKILL coding and layout automation
  • Work across IP, chip-top and cross-layer integration (CMOS + GaN)

Hourly Rate: $100-115 based on experience

Please submit your resume to careers@mojo.vision

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